1. Field of the Invention
The present invention relates to a memory integrated circuit, and more particularly, to a voltage boosting power supply circuit for regulating the charge amount supplied to a memory circuit.
The present application is based on Korean Patent Application No. 97-15003 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
In general, as the capacitance in memory integrated circuits increases, the need for supplying a voltage boosting power supply to the memory circuits for activating word lines in the memory cells increases.
FIG. 1 is a circuit diagram of a conventional voltage boosting power supply circuit for a memory integrated circuit. Referring to FIG. 1, the conventional voltage power supply circuit includes a buffer 11, a voltage booster 13 and a transmitter 15. The voltage booster 13 includes an NMOS transistor 31 and three capacitors 21, 23 and 25, where capacitor 21 is deactivated and capacitors 23,35 are coupled in parallel between buffer 11 and transmitter 15.
When the charge amount of the conventional voltage boosting power supply is more than that consumed in the output terminal of the transmitter, the reliability of the memory integrated circuit chip may malfunction. Similarly, when the charge amount of the voltage boosting power supply of the voltage booster is less than that consumed in the output of the transmitter, the memory integrated circuit chip is reduced. Accordingly, it is desired to adjust the charge supplied by the voltage boosting power supply to closely match the charge consumed.
FIG. 2A shows an alteration of the circuit of FIG. 1 for reducing the charge amount of a voltage boosting power supply Vpp. FIG. 2B shows another alteration of the circuit of FIG. 1 for increasing the charge amount of the voltage boosting power supply Vpp.
Comparing FIGS. 2A and 2B, the amount of charge from the voltage boosting power supply is reduced or increased depending upon the connection state of input and output terminals of the capacitors 21 and 25. Changing the connection states of the metal lines leads of the capacitors 21,25 requires that the masking process and lithography process be re-performed. Doing so, however, requires great cost and delays development of the integrated circuit chip.
Accordingly, the need remains for a more efficient method and structure for controlling such charge amount.